1. Field of Invention
The invention relates to a display apparatus and, in particular, to a flat display apparatus having a scan driving circuit.
2. Related Art
With the advantages such as low power consumption, less heat generation, lightness and less radiation, flat display apparatuses have been applied to various electronic products and gradually take the place of cathode ray tube (CRT) display apparatuses. Among the technologies of flat display apparatuses (e.g. LCD apparatus), the GOP (gate driver on panel) technology is used to form the components of the scan driver directly on the glass panel by a TFT (thin-film transistor) process, saving the cost of the scan driver IC. Currently, the GOP technology is mostly applied to the dual-sided driving display apparatus, which have two GOP circuits (i.e. scan driving circuits) on the left and right sides of the display area respectively lest the driving signals of the scan driving circuit of the single-sided large-scale display apparatus should diminish due to the higher resistance caused by the longer signal transmission distance.
FIG. 1 is a schematic block diagram of a conventional scan driving circuit 1 of a display apparatus. As shown in FIG. 1, the scan driving circuit 1 includes a clock generator CK, a first stage of driving unit 11, a second stage of driving unit 12, . . . , and an mth stage of driving unit 1m. The clock generator CK can alternately generate two clock signals CK1 and CK2. The clock signal CK1 leads the clock signal CK2 by a certain phase. The clock signals CK1 and CK2 are both inputted to the first stage of driving unit 11, second stage of driving unit 12, . . . , and mth stage of driving unit 1m. Besides, the first stage of driving unit 11 further receives an initial signal IN (such as a vertical synchronization signal, STV), and outputs an output signal OUT1. The output signal OUT1 can drive a row of pixel units and also can be used as the initial signal of the second stage of driving unit 12. In other words, the output signals of every stage of driving unit are used to be both of the driving signal of a row of pixel units and the initial signal of the next stage of driving unit. Thereby, an output signal OUTk (1≦k≦m) can be sequentially outputted by the first stage of driving unit 11, second stage of driving unit 12, . . . , and mth stage of driving unit 1m, used as the scan signal of the display apparatus. The scan signal is inputted to the gate of the driving transistor (such as a TFT) of the pixel to turn on or turn off the driving transistor, and thereby the display apparatus can display images in cooperation with the input of the data signal.
FIGS. 2A and 2B are schematic waveform diagrams of the clock signals CK1 and CK2 in FIG. 1 and the output signal of kth stage of driving unit 1k (1≦k≦m). To achieve the sufficient driving force, the last driving component (such as TFT) is usually configured with a considerably large size, and accordingly the accompanying parasitic capacitance (Cgd) is also considerably large. Therefore, as shown in FIG. 2, when the clock CK2 has a level transition (i.e. from a lower level to a higher lever or reversely), a rising or falling ripple (can be regarded as a noise) will be generated on the gate of the TFT due to the signal coupling effect. Moreover, a falling or rising ripple will be also generated on the gate of the TFT due to the signal coupling effect when the clock signal CK1 has a level transition. Besides, when the clock signal CK2 is changed from a lower level to a higher level, a current leakage path will formed in the last driving component (e.g. TFT), resulting in a larger ripple. Accordingly, for the conventional art, the falling ripple caused by the level transition of the clock signal CK1 decouples the rising ripple caused by the level transition of the clock signal CK2 during a data input period, and thereby the noise of the output signal OUTk at the timing t1, t2, t3, . . . in FIG. 2A is eliminated.
However, as shown in FIG. 2B, for a conventional display apparatus, the clock signal CK2 will not be counteracted by the clock signal CK1 of the previous phase during the beginning of the initial data input period Td or a blanking time Tb of every image because the clock signal CK1 doesn't appear thereat. Therefore, the output signal OUTk will have a high-level ripple voltage Vp, due to the signal coupling and current leakage effects caused by the level transition of the clock signal CK2, at the timing Tp1, Tp2, . . . as shown in FIG. 2B (i.e. the timing of the first appearing clock signal CK2 after the data input period begins and the timing within the blanking time Tb) after a frame time T of every image begins. Moreover, all the driving units 1k (1≦k≦m) electrically connected to the clock signal CK2 will also be influenced likewise.
Accordingly, when the output signal OUTk with the high-level ripple voltage is inputted to the gate of the driving transistor, the levels of the gate and source of the driving transistor will be really close to each other, meaning the voltage difference (i.e. Vgs) becomes less. If the voltage difference between the gate and the source is greater than the threshold voltage (i.e. Vgs>Vth), the driving transistor will be turned on. Thus, the pixel voltage will be subjected to a current leakage, and accordingly the display apparatus will display erroneously (e.g. with bright or dark lines).
Therefore, it is an important subject to provide a display apparatus that can avoid the current leakage of the pixel voltage due to the signal coupling and current leakage effects and thus avoid erroneous display.